Graeme Cunningham


SoC functional verification

Motorola 02 (2000-04)

Research Engineer: Graeme Cunningham
Sponsor: Motorola
Academic Supervision: Dr Paul Jackson, University of Edinburgh

As the complexity of SoC designs continue to grow, the verification effort needed to validate the correct functionality of these devices expands even more rapidly. Today verification is considered a task that is of equal, or even greater, effort to design – and the proportion of overall effort is steadily increasing. Hence, as in the design realm, the abstraction level must be raised to allow full functional verification to continue.

The project will investigate current high-level verification tools, flows, and methodologies, utilising real examples of complex system-level verification tasks. Aims to compare and contrast the various options currently in use, whilst highlighting any limitations on future use and any desirable features or enhancements that may be of benefit. Object-orientated methodology will be a guiding principle throughout the investigation, as will the aims of verification environment extensibility and reuse. The applicability of modern high-level (or system-level) design techniques to the verification problem will be examined.
The first verification test-case considered will be that of an integrated RapidIO switch/bridge – this will provide an example of the complexities encountered in modern SoC designs. Issues to be investigated will include methods of verification for complex logic blocks (or virtual components, VCs) with multiple embedded finite-state machines, the on-chip interfaces between these VC’s, bus-based interface verification with on-chip and off-chip arbitration, and interfaces to packet-based interconnect architectures. Extrapolation of these techniques, and others, will be investigated for future SoC designs with embedded processor/controller VCs.

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