Mixed-signal optimisation for SoC based mobile terminal architectures
Epson 02 (2001-05)
Research Engineer: Michael Osoba
Sponsor: Epson Scotland Design Centre
Academic Supervision: Dr James Irvine and Prof Bob Stewart,
University of Strathclyde
Semiconductor vendors like Epson are increasingly expected by mobile phone vendors to provide them with core functionality for standardised baseband mobile components, like the speech coder, as part of their product offering (either silicon or IP blocks). Such integrated devices often incorporate DSP cores, a microcontroller core, logic functions and analogue functions in the same device (System-on-Chip).
The project will investigate the development methodologies and design issues associated with mixed signal design for SoC, starting with a review of best practice from the published literature. The target application is next generation mobile phones (especially the emerging 3G – UMTS), and the focus of the research will be the analog interface between symbol rate and chip-rate processing. Of particular interest is the development of the analog integration technology that is required to provide highly stable, reproducible and balanced (I-Q) broadband analogue components.
DSP algorithmic and analogue simulations will be studied and appropriate small-signal models of the analogue component functionality developed. Special attention may also be given to issues such on-chip mixed signal testing, optimised chip layout for minimising the interaction between small-signal analog and high-speed digital cores, and the requirement for the integration of co-design (analogue and digital) design methodologies for SoC.
Leading-edge combined algorithm and hardware design tools will be used as the research platform, along with Epson process technology and mobile baseband development projects planned at the Scotland Design Centre.
Project work will be undertaken in association with other Epson Design Centres in Europe and Japan.
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